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Tektronix 4-SREMBD Computer analysis and triggering license - kopi

Adds Embedded triggering and analysis

NOK 19 260,- (eks. mva.)

Installed Option; Embedded serial triggering and analysis (I2C, SPI)
Produktnummer: 4-SRCOMP

Serial protocol triggering and analysis (optional)

During debugging, it can be invaluable to trace the flow of activity through a system by observing the traffic on one  or more serial buses. It could take many minutes to manually decode a single serial packet, much less the thousands of packets that may be present in a long acquisition.

The 4 Series MSO offers a robust set of tools for working with the most common serial buses found in embedded design including I2C, SPI, I3C, RS-232/422/485/UART, SPMI, CAN, CAN FD, LIN, FlexRay, SENT, USB LS/FS/HS, Ethernet 10/100, Audio (I2S/LJ/RJ/TDM), MIL-STD-1553, and ARINC 429.

Serial protocol search enables you to search through a long acquisition of serial packets and find the ones that contain the specific packet content you specify. Each occurrence is highlighted by a search mark. Rapid navigation
between marks is as simple as pressing the Previous ( ← ) and Next ( → ) buttons on the front panel or in the Search badge that appears in the Results Bar.

The tools described for serial buses also work on parallel buses. Support for parallel buses is standard in the 4 Series MSO. Parallel buses can be up to 48 bits wide and can include a combination of analog and digital channels.

And if you know the event of interest that you are attempting to capture occurs when a particular command is sent across a serial bus, wouldn't it be nice if you could trigger on that event? Unfortunately, it's not as easy as simply specifying an edge or a pulse width trigger.

  • Serial protocol triggering lets you trigger on specific packet content including start of packet, specific addresses, specific data content, unique identifiers, and errors.
  • Bus waveforms provide a higher-level, combined view of the individual signals (clock, data, chip enable, and so on) that make up your bus, making it easy to identify where packets begin and end, and identifying
    sub-packet components such as address, data, identifier, CRC, and so on.
  • The bus waveform is time aligned with all other displayed signals, making it easy to measure timing relationships across various parts of the system under test.
  • Bus decode tables provide a tabular view of all decoded packets in an acquisition much like you would see in a software listing. Packets are time stamped and listed consecutively with columns for each component (Address, Data, and so on).