JTAG Boundary Scan test
At JTAG Technologies we are proud to say that we are boundary-scan. Since the early 1990s we have lived and breathed the technology that has revolutionised the manufacture and test of digital and mixed signal Printed Circuit Board Assemblies (PCBA's) the world over.
Test solutions for today's electronics
DESIGN - Get new board and system designs up and running
PRODUCTION - Complete your production line with JTAG
SERVICE - Repair boards even when no design data is available
What is Boundary-scan?
Boundary-scan (also known as JTAG boundary-scan) is a method of testing modern Printed Circuit Boards (PCBs) after assembly. Using the dedicated test logic built into many of today’s integrated circuits (ICs), boundary-scan checks if each device is correctly inserted and soldered onto the PCB.
Typical devices that incorporate boundary-scan technology include CPLDs, FPGAs, microprocessors, DSPs, ASICs, bus logic, SERDES, telecom encoders, PHYs and Bridges (PCI/PCIe).
A number of device manufacturers embracing boundary-scan technology are Intel, Analog Devices, ARM, Freescale, NXP, PLX, ST, TI, Renesas, Xilinx, Altera, Lattice, Broadcom and Actel among others.
Boundary-scan enabled devices feature four (or sometimes five) dedicated test access port (TAP) signals:
- TCK (Test Clock)
- TMS (Test Mode Select)
- TDI (Test Data In)
- TDO (Test Data Out)
- TRST (Test Logic Reset) (optional)
To simplify the test infrastructure within a PCB it is common to connect the devices in a serial (daisy chain) formation so that the first device's TDO connects to the next device’s TDI (and so on) to form a so-called scan chain.
To activate the boundary-scan logic, simply pulse TCK while toggling TMS as specified in the TAP state machine map. Once activated, boundary-scan logic controls the device's pins while isolating the primary core functions of the device.